A floating point number can be expressed as follows:±1.x*2y 
where: x=fraction                1.x=significand (also known as the mantissa)        y=exponent        
A floating point number hence consists of three components, namely a sign component, an exponent component and a fraction component (which can be converted to a significand component). The sign component is typically a 1-bit field, which is set to “0” for a positive number, and to “1” for a negative number. The number of bits used for the exponent component and fraction component will vary depending on whether the floating point numbers are single precision numbers or double precision numbers, but can be given by the following table:
TABLE 1Number of bits inNumber of bits inPrecisionexponentExponent biasfractionSingle8+127 23Single-extended>=11Unspecified>=31Double11+102352Double-extended>=15unspecified>=63
A number of known techniques have been used for comparing two floating point operands to determine which operand is larger. A first known technique involves the comparison of the complete operands (with the exception of the sign bits) in the format specified in Table 1 above, with special handling for NaNs (Not-a-Number values).
This technique is used to determine which operand is larger in situations where both floating point operands are of the same sign, and takes advantage of the fact that two floating point values with the same sign may be compared as unsigned 2's complement integers for equality and relative magnitude. This fails only for NaNs, which must compare as unordered and not relative to non-NaN values.
Logic to perform this comparison may take several forms. FIG. 1 illustrates one such form of logic, in which two adders 30, 40 are used. Bits [n-2:0] of the n-bit floating point operand A 10 (i.e. all bits other than the sign bit) are passed directly to one input of adder 30 whilst bits [n-2:0] of the other operand B 20 are negated prior to supply to the other input of this adder 30. The second adder 40 in contrast takes as inputs A[n-2:0] negated and B[n-2:0] without negation. Both adders have the carry-in bit set, and the relative magnitude and equality may be determined form the carry-out bits of both adders (labelled AgtB and BgtA in FIG. 1) according to the following table:
TABLE 2ConditionA + ~B + 1~A + B + 1A == B10000 . . . 000010000 . . . 0000A > B if signs positive1δ, δ != 00β, β != 0B > A if signs negativeA < B if signs positive0δ, δ != 01β, β != 0B < A if signs negative
In the above table, the far left bit in the centre column is the AgtB indication and the far left bit in the right column is the BgtA indication. The following code segment illustrates how the result of the comparison operation is determined based on these two indications:    if (AgtB and BgtA) A and B are equal    if (sign is positive)            if (AgtB and ˜BgtA) A is greater than B        else B is greater than A            else (sign is negative)            if (AgtB and ˜BgtA) B is greater than A (it is less negative, hence greater in absolute magnitude)        else A is greater than B        
Hence, when the floating point operands both have positive signs, if the carry-out bit AgtB from adder 30 is set (i.e. has a logic 1 value), and the carry-out bit BgtA from adder 40 is not set (i.e. has a logic 0 value), this indicates that operand A is greater than operand B, whilst if the carry-out bit AgtB from adder 30 is not set, and the carry-out bit BgtA from adder 40 is set, this indicates that operand B is greater than operand A. Alternatively, when the floating point operands both have negative signs, then if the carry-out bit AgtB from adder 30 is set (i.e. has a logic 1 value), and the carry-out bit BgtA from adder 40 is not set (i.e. has a logic 0 value), this indicates that operand B is greater than operand A, whilst if the carry-out bit AgtB from adder 30 is not set, and the carry-out bit BgtA from adder 40 is set, this indicates that operand A is greater than operand B.
If both AgtB and BgtA are set then, irrespective of whether the signs are positive or negative, this indicates that the operands A and B are equal.
Sign evaluation and NaN detection must be performed on the input operands. If either operand is a NaN the result is only UNORDERED, not equal (regardless of the fraction of the NaN or NaNs) and no other comparison is valid. If the signs are different and neither operand is a NaN the result will be GREATERTHAN or LESSTHAN, and no further comparison of bits is required. This detection can be performed in parallel with the additions discussed above with reference to FIG. 1, and used to override the final compare results. Logic combines the NaN detection and the AgtB and BgtA signals to produce the comparison result.
An alternative prior art technique to that described above with reference to FIG. 1 considers each component of the operands independently. Hence, in accordance with this technique the signs, exponents and fractions (or significands) are considered independently. The following sequence of operations illustrates this method (assuming the outputs are UNORDERED, EQUAL, GREATERTHAN, and LESSTHAN):    if (AisNaN|BisNaN)            A or B is NaN, only UNORDERED is signalled        signal UNORDERED            else if (AisZero & BisZero)            A and B are zeros, compare is equal regardless of signs        signal EQUAL            else if (˜Asign & Bsign)            A is greater than B by virtue of signs (A is positive and B is negative)        signal GREATERTHAN            else if (Asign & ˜Bsign)            A is less than B by virtue of signs (A is negative and B is positive)        signal LESSTHAN            else if (Aexp>Bexp)            A is greater than B by virtue of exponent        signal GREATERTHAN            else if (Bexp>Aexp)            A is less than B by virtue of exponents        signal LESSTHAN            else if (Afraction>Bfraction)            A is greater than B by virtue of fractions        signal GREATERTHAN            else if (Bfraction>Afraction)            A is less than B by virtue of fractions        signal LESSTHAN            else            A and B are equal by virtue of sign, exponent and fraction        signal EQUAL        
As can be seen from FIG. 2, the sign bits Asign and Bsign pass directly to the comparison evaluation block. Exponent evaluation block 110 detects whether either exponent is zero or is a maximum value and produces signals indicative of that analysis. Adder 115 receives the exponent of operand A and the negated version of the exponent of operand B and adds these values together with a carry-in of +1, such that the carry-out from the adder 115 indicates whether the exponent of A is greater than the exponent of B. Adder 120 performs a similar computation but with the exponent of operand A negated and the exponent of operand B not negated, and hence produces a carry-out signal indicating whether the exponent of B is great than the exponent of A. Adders 130 and 135 operate in a analogous manner to adders 115 and 120, but receive the fraction components as inputs instead of the exponent components, and hence produce one output indicating whether the fraction of operand A is greater than the fraction of operand B, and another output indicating whether the fraction of operand B is greater than the fraction of operand A. Finally, logic 125 detects whether either fraction is zero and outputs signals indicative of that analysis.
The comparison evaluation logic block 140 receives all of the above mentioned signals as illustrated in FIG. 2 and performs the evaluation of those signals in accordance with the logic flow above.
Both of the prior art techniques discussed above with reference to FIGS. 1 and 2 are useful ways of implementing a floating point comparison operation in a pipelined processor in which the comparison must be performed fully in a fixed number of stages. However, in some situations, the requirement for the comparison to be performed fully in a fixed number of stages can be removed, and in such situations it would be desirable to provide an improved technique for comparing floating point operands which consumes less power and/or produces the comparison result more quickly.